Semiconductor integrated circuit (IC) technology has experienced rapid progress including the continued minimization of feature sizes and the maximization of packing density. The minimization of feature size relies on improvement in photolithography and its ability to print smaller features or critical dimensions (CD). This is further related to film deposition process and wafer alignment during lithography process. To improve the photolithography and film patterning accuracy, it is needed to measure the overlay mark errors generated from the wafer bending and/or deformation that may be caused by film deposition, thermal treatment, clamping (chucking) during wafer transferring, and other factors. However, after one or more film layers are deposited over the patterned layer, it may become difficult to measure the overlay marks on the patterned layer using the existing inspection tool.
Therefore, an apparatus for lithography patterning and a method utilizing the same are needed to address the above issues associated with overlay mark inspections.